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1 of 23 gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 gs7025 pro-linx? serial digital receiver www.gennum.com key features ? smpte 259m-c compliant (270mb/s) ? automatic cable equalization (typically greater than 350m of high-quality cable) ? serial data outputs muted and serial clock remains active when input data is lost ? operation independent of sav/eav sync signals ? signal strength indicator output ? carrier detect with programmable threshold level ? power savings mode (output serial clock disable) ? large ijt, typically 0.56ui beyond loop bandwidth ?robust lock detect applications cable equalization plus clock and data recovery for all high speed serial digital interface applications involving smpte 259m-c. description the gs7025 provides automatic cable equalization and high-performance clock and data recovery for serial digital signals. the gs7025 receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at pecl levels (800mv). the onboard cable equalizer provides up to 35db of gain at 135mhz, which typically results in equalization of greater than 350m of high-quality cable at 270mb/s. the gs7025 requires only one external resistor to set the vco centre frequency and provides adjustment free operation. the gs7025 has dedicated pins to indicate signal strength, carrier detect, and lock. optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. in addition, the gs7025 provides an 'output eye monitor test' (oem_test) for diagnostic testing of signal integrity after equalization, prior to re-slicing. the serial clock outputs can be disabled to reduce power. the gs7025 operates from a single +5v or -5v supply. gs7025 functional block diagram lf+ lfs lf- cbg r vco carrier detect phaselock harmonic frequency acquisition vco lock sdo sdo clk_en sco sco mute c osc phase detector logic + - sdi sdi oem_test agc cap cd_adj auto eq control eye monitor variable gain eq stage charge pump + - + - ssi/cd a/d analog digital mux ddi ddi
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 2 of 23 revision history contents key features................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 revision history ............................................................................................................... ..................................2 1. pin out..................................................................................................................... ..........................................3 1.1 gs7025 pin assignment ..................................................................................................... ............3 1.2 gs7025 pin descriptions ................................................................................................... .............4 2. electrical characteristics .................................................................................................. ..........................5 2.1 absolute maximum ratings .................................................................................................. ........5 2.2 dc electrical characteristics ............................................................................................. ...........5 2.3 ac electrical characteristics ............................................................................................. ...........6 2.4 typical performance curves ................................................................................................ ........8 3. detailed description........................................................................................................ .......................... 10 3.1 cable equalizer ........................................................................................................... ................... 10 3.1.1 signal strength indication/carrier detect ................................................................ 10 3.1.2 carrier detect threshold adjust................................................................................... 11 3.1.3 output eye monitor test................................................................................................. 1 1 3.2 reclocker ................................................................................................................. ......................... 12 3.2.1 phase locked loop (pll)................................................................................................. 1 2 3.2.2 frequency acquisition.................................................................................................... .13 3.2.3 logic circuit ............................................................................................................ ............ 14 3.2.4 locking.................................................................................................................. ................ 14 3.2.5 output data muting....................................................................................................... ... 16 3.2.6 clock enable............................................................................................................. ........... 16 3.2.7 stressful data patterns.................................................................................................. ... 16 3.3 i/o description ........................................................................................................... .................... 16 3.3.1 high speed analog inputs (sdi/sdi )........................................................................... 16 3.3.2 high speed outputs (sdo/sdo and sco/sco )...................................................... 18 4. application information ..................................................................................................... ..................... 19 4.1 typical application circuit ............................................................................................... ......... 19 5. package & ordering information .............................................................................................. ............ 20 5.1 package dimensions ........................................................................................................ ............. 20 5.2 solder reflow profiles .................................................................................................... .............. 21 5.3 ordering information ...................................................................................................... ............. 21 version ecr pcn date changes and/or modifications 7 152762 ? october 2009 c onverted document to new format. c hanged part numbers in 5.3 ordering information .
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 3 of 23 1. pin out 1.1 gs7025 pin assignment figure 1-1: gs 7025 pin out sdo sdo v ee sco sco v ee n c n c rsv1 n c gs7025 top view agc+ v cc v ee lf+ lfs lf- v ee r vco _rtn r vco cbg v cc ddi ddi v cc_75 v cc v ee sdi sdi v cc v ee cd_adj agc- v cc_75 oem_test mod a/d ssi/cd lock c osc v ee clk_en v cc v ee v ee 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 2 6 25 24 23 12 13 14 15 1 6 17 18 19 20 21 22 44 43 42 41 40 39 38 37 3 6 35 34
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 4 of 23 1.2 gs7025 pin descriptions table 1-1: gs7025 pin descriptions pin number name ty p e description 1, 2 ddi/ddi i digital data inputs (differential e c l/pe c l). 3, 44 v cc _75 i power supply connection for internal 75 pullup resistors connected to ddi/ddi . 4, 8, 13, 22, 35 v cc i most positive power supply connection. 5, 9, 14, 18, 27, 30, 33, 34, 37 v ee i most negative power supply connection. 6, 7 s di/ s di i differential analog data inputs. 10 c d_ad j i c arrier detect threshold adjust. 11, 12 a gc -, a gc + i external a gc capacitor. v common mode = 2.7v typ. 15, 16, 17 lf+, lf s , lf- i loop filter component connection. 19 r v c o _rtn i r v c o return. frequency setting resistor return connection. 20 r v c o i frequency setting resistor connection. 21 c b g i internal bandgap voltage filter capacitor. 23, 25, 26 nc - no connect - do not connect to power or ground. leave floating. 24 r s v1 i reserved pin 1. always set hi g h. 28, 29 sc o / sc oo s erial clock output. sc o / sc o are differential current mode outputs and require external 75 pullup resistors. 31, 32 s do / s do o equalized and reclocked serial digital data outputs. s do / s do are differential current mode outputs and require external 75 pullup resistors. 36 c lk_en i c lock enable. when hi g h, the serial clock outputs are enabled. 38 c o sc i timing control capacitor for internal system clock. 39 lo c k o lock indication. when hi g h, the gs 7025 is locked. lo c k is an open collector output and requires an external 10k pullup resistor. 40 ss i/ c do s ignal strength indicator/ c arrier detect. 41 a/d i analog/digital select. 42 mod i 270 mb/s modulus select - always set hi g h. 43 oem_te s t o output ?eye? monitor test. s ingle-ended current mode output that requires an external 50 pullup resistor. this feature is recommended for debugging purposes only. if enabled during normal operation, the maximum operating temperature is rated to 60 c . for maximum cable length performance the oem_te s t must be disabled.
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 5 of 23 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value s upply voltage (v s )5.5v input voltage range (any input) v cc + 0.5 to v ee - 0.5v operating temperature range 0 c t a 70 c s torage temperature range -65 c t s 150 c lead temperature (soldering, 10 sec) 260 c moisture s ensitivity level 3 table 2-1: dc electrical characteristics v cc = 5.0v, ta = 0 ? 70 c unless otherwise stated, rlf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter condition min ty p i c a l 1 max units note s test level s upply voltage 4.75 5 5.25 v 3 s upply c urrent c lk_en = 0 - 115 - ma 9 c lk_en = 1 - 125 - ma 3 s di c ommon mode voltage -2.4-v 3 ddi/ddi c ommon mode input voltage range v ee +(v diff /2) 0.4 to 4.6 v cc -(v diff /2) v 2 3 ddi/ddi differential input drive 200 800 2000 mv 3 ss i/ c d output c urrent hi g h, om oh = -10a -3-v 3 hi g h, 300m oh = -10a -2.1-v 3 oem_te s t bias potential 50 -4.75-v43 a/d input voltage hi g h2.3 - - v 3 low - - 0.8
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 6 of 23 2.3 ac electrical characteristics r s v1, in _enable input voltage hi g h2.0 - - v 3 low - - 0.8 c lk_en input voltage hi g h2.5 - - v 3 low - - 0.8 lo c k output low voltage i ol = 500a 0.25 0.4 v 3 1 c lk_en s ource c urrent low, v il =0v -2655a 1 note s : 1. typical - measured on characterization board. 2. v diff is the differential input signal swing. 3. lock is an open collector output and requires an external pullup resistor. 4. if oem_test is permanently enabled, operating temp erature range is limited from 0c to 60c inclusive. te s t level s : 1. production test at room temperature and nominal supply voltage with guardba nds for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correl ated test. 3. production test at room temper ature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/ch aracterization data of similar product. 9. indirect test. table 2-1: dc electrical characteristics v cc = 5.0v, ta = 0 ? 70 c unless otherwise stated, rlf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter condition min ty p i c a l 1 max units note s test level table 2-2: ac electrical characteristics v cc = 5.0v, vee = 0v, ta = 0 ? 70 c unless otherwise stated, rlf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter condition min ty p i c a l 1 max units note s test level s erial data rate s di - 270 (only) - mb/s 3 maximum equalizer g ain (see figure 3) @ 135mhz - 35 - db 6 additive j itter [pseudorandom (2 23 -1)] 270mb/s, 300m (belden 8281) - 300 - ps p-p 2, 7 9 intrinsic j itter [pseudorandom (2 23 -1)] 270mb/s - 185 - ps p-p 2, 6 4 intrinsic j itter [pathological ( s di checkfield)] 270mb/s - 462 - ps p-p 2, 6 3
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 7 of 23 input j itter tolerance 270mb/s 0.40 0.56 - ui p-p 3, 6 9 lock time - s ynchronous s witch t switch < 0.5s, 270mb/s -1 -s47 0.5s< t switch <10ms -1 -ms t switch > 10 ms - 4 - ms s do mute time 0.5 1 2 s 5 7 s do to sc o s ynchronization -200 0 200 ps 7 s do, sc o output s ignal s wing 75 d c load 600 800 1000 mv p-p 1 s do, sc o rise & fall times 20%-80% 200 300 400 ps 7 s di/ s di input resistance - 10 - k 76 s di/ s di input c apacitance - 1.0 - pf 7 6 c arrier detect response time c arrier applied - 3 - s 7, 8 6 c arrier removed -30- note s : 1. typical - measured on characterization board. 2. characterized 6 sigma rms. 3. ijt measured with sinusoidal modulation beyond loop bandwidth (at 6.5mhz). 4. synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie . line 10 switching for component ntsc). 5. carrier loss time refers to the response of the sdo output from valid re-clocked input data to mute mode when the input signa l is removed. 6. using the ddi input, a/d =0. 7. using the sdi input, a/d =1. 8. carrier detect response time refers to the response of the ssi/cd output from a logi c high to a logic low state when the inpu t signal is removed or amplitude drops below the threshold set by the cd_adj pin. ssi/cd pin loading c l <50pf, r l =open cct. te s t level s : 1. production test at room temperature and nominal supply voltage with guardba nds for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correl ated test. 3. production test at room temper ature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/ch aracterization data of similar product. 9. indirect test. table 2-2: ac electrical characteristics v cc = 5.0v, vee = 0v, ta = 0 ? 70 c unless otherwise stated, rlf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter condition min ty p i c a l 1 max units note s test level
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 8 of 23 2.4 typical performance curves (vs = 5v, ta = 25c unless otherwise shown) figure 2-1: test setup for figure 2-5 and figure 2-6 figure 2-2: ss i/ c d voltage vs. c able length (belden 8281) ( c d_ad j = 0v) figure 2-3: equalizer g ain vs. frequency characterization board gs9028 cable driver tektronix gi g abert 1400 analyzer tektronix gi g abert 1400 transmitter belden 8281 cable data data clock trigger 0 50 100 150 200 250 300 350 400 450 500 5.00 4.50 4.00 3.50 3.00 2.50 cable length (m) ssi/cd output voltage (v) 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1000 gain ( d b) frequency (mhz)
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 9 of 23 figure 2-4: c arrier detect adjust voltage threshold c haracteristics figure 2-5: typical additive j itter vs. input c able length (belden 8281)pseudorandom (2 23 -1) figure 2-6: intrinsic j itter (2 23 - 1 pattern) 270mb/s 5.0 4.5 4.0 3.5 3.0 2.5 2.0 200 250 300 350 400 cable length (m) cd_adj voltage (v) j itter (ps p-p) c able len g th (m) 450 400 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 270mb/s ( c haracterized)
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 10 of 23 figure 2-7: typical i j t vs. temperature (v cc = 5.0v) ( c haracterized) 0.200 0.250 0.300 0.350 0.400 0.450 0.500 0.550 0. 6 00 0 1020304050 6 070 temperature (c) ijt (ui) 270m b /s
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 11 of 23 3. detailed description the gs7025 serial digital receiver is a bipolar integrated circuit, containing a built-in cable equalizer and reclocker. serial digital signals are applied to either the analog sdi/sdi or digital ddi/ddi inputs. signals applied to the sdi/sdi inputs are equalized and then passed to a multiplexer. signals applied to the ddi/ddi inputs bypass the equalizer, and go directly to the multiplexer. the analog/digital select pin (a/d ) determines which signal is then passed to the reclocker. packaged in a 44 pin mqfp, the receiver operates from a single 5v supply at a data rate of 270mb/s. typical power consumption is 600mw. 3.1 cable equalizer the automatic cable equalizer is designed to equalize a serial digital data rate of 270mb/s. the serial data signal is connected to the input pins (sdi/sdi ) either differentially or single-endedly. the input signal passes through a variable gain equalizing stage, whose frequency response closely matches the inverse cable loss characteristic. in addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. the gain stage provides up to 35db of gain at 135mhz which typically results in equalization of greater than 350m of belden 8281 cable at 270mb/s. the edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. this error signal is integrated by an external differential agc filter capacitor (agc+/agc-) providing a steady control voltage for the gain stage. as the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. the equalized signal is dc-restored, effectively restoring the logic threshold of the equalized signal to its corrective level irrespective of shifts due to ac-coupling. 3.1.1 signal strength indication/carrier detect the gs7025 incorporates an analog signal strength indicator/carrier detect (ssi/cd) output indicating both the presence of a carrier and the amount of equalization applied to the signal. the voltage output of this pin versus cable length (signal strength) is shown in figure 2-2 and figure 3-1 . with 0m of cable (800mv input signal levels), the ssi/cd output voltage is approximately 4.5v. as the cable length increases, the ssi/cd voltage decreases linearly providing accurate correlation between the ssi/cd voltage and cable length.
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 12 of 23 figure 3-1: ss i/ c d voltage vs. c able length when the signal strength decreases to the level set at the ?carrier detect threshold adjust? pin, the ssi/cd voltage goes to a logic ?0? state (0.8 v) and can be used to drive other ttl/cmos compatible logic inputs. when loss of carrier is detected, the sdo/sdo outputs are muted (set to a known static state). additional ssi/cd output source current can be obtained in applications with a pull-up resistor. an external 5k pull-up resistor with less than 50pf capacitor loading is recommended. 3.1.2 carrier detect threshold adjust carrier detect threshold adjust is designed applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. the gs7025 solves this problem with a user adjustable threshold which meets the unique conditions that exist in each application. override and internal default settings are provided to give the user total flexibility. the threshold level at which loss of carrier is detected is adjustable via external resistors at the cd_adj pin (see figure 2-4 ). the control voltage at the cd_adj pin is set by a simple resistor divider circuit (see figure 4-1: gs7025 typical application circuit ). the threshold level is adjustable from 200m to 350m. by default (no external resistors), the threshold is typically 320m. in noisy environments, it is not recommended to leave this pin floating. connecting this pin to vee disables the sdo/sdo muting function and allows for maximum possible cable length equalization. 3.1.3 output eye monitor test the gs7025 also provides an 'output eye monitor test' (oem_test) which allows the verification of signal integrity after equalization, prior to re-slicing. the oem_test pin is an open collector current output that requires an external 50 pullup resistor. when the pullup resistor is not used, the oem_test block is disabled and the internal oem_test circuit is powered down. the oem_test provides a 100mvp-p signal when driving a 50 oscilloscope input. due to additional power consumed by this diagnostic circuit, it is not recommended for continuous operation. 0 1 2 3 4 5 50 100 150 200 250 300 350 400 450 500 ssi/cd output voltage (v) cable length (m) 0 cd_adj control range
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 13 of 23 note: for maximum cable length performance the oem_test block should be disabled. 3.2 reclocker the reclocker receives a differential serial data stream from the internal multiplexer. it locks an internal clock to the incoming data. it outputs the differential pecl retimed data signal on sdo/sdo . it outputs the recovered clock on sco/sco . the timing between the output and clock signals is shown in figure 3-2 . figure 3-2: output and c lock s ignal timing the reclocker contains three main functional blocks: the phase locked loop, frequency acquisition, and logic circuit. 3.2.1 phase locked loop (pll) the phase locked loop locks the internal pll clock to the incoming data rate. a simplified block diagram of the pll is shown in figure 3-3 below. the main components are the vco, the phase detector, the charge pump, and the loop filter. figure 3-3: s implified block diagram of the pll sdo sco 50 % ddi/ddi lf+ lfs lf- r vco vco r lf c lf1 c lf2 2 phase detector internal pll clock charge pump loop filter
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 14 of 23 3.2.1.1 vco the vco is a differential low phase noise, factory trimmed oscillator that provides increased immunity to pcb noise and precise control of the vco centre frequency. the vco has a pull range of 15% about the centre frequency. a single low-impedance external resistor, rvco, sets the vco centre frequency. the low-impedance rvco minimizes thermal noise and reduces the pll's sensitivity to pcb noise. the recommended rvco value for smpte 259m-c applications is 365 . when the input data stream is removed for an excessive period of time (see ac electrical characteristics table), the vco frequency can drift from the 270mb/s centre frequency to the limits shown in table 3-1 . 3.2.1.2 phase detector the phase detector compares the phase of the pll clock with the phase of the incoming data signal and generates error correcting timing pulses. the phase detector design provides a linear transfer function which maximizes the input jitter tolerance of the pll. 3.2.1.3 charge pump the charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. a unique differential charge pump design insures that the output phase does not drift when data transitions are sparse. this makes the gs7025 ideal for smpte 259m-c applications where pathological signals have data transition densities of 0.05. 3.2.1.4 loop filter the loop filter integrates the charge pump packets and produces a vco control voltage. the loop filter is comprised of three external components which are connected to pins lf+, lfs, and lf-. the loop filter design is fully differential giving the gs7025 increased immunity to pcb board noise. the loop filter components are critical in determining the loop bandwidth and damping of the pll. recommended values for smpte 259m-c applications are shown in the gs7025 typical application circuit . no further changes from the recommended gs7025 loop filter components are necessary. for more information on choosing loop filter component values, refer to the pll design guidelines section of the gs9025a data sheet. table 3-1: frequency drift range frequency min (%) max(%) 270mb/s lock -13 28
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 15 of 23 3.2.2 frequency acquisition the core pll is able to lock if the incoming data rate and the pll clock frequency are within the pll capture range (which is slightly larger than the loop bandwidth). to assist the pll to lock, the gs7025 uses a frequency acquisition circuit. the frequency acquisition circuit sweeps the vco control voltage so that the vco frequency changes from -10% to +10% of the centre frequency. figure 3-4 shows a typical sweep waveform. figure 3-4: typical s weep waveform the vco frequency starts at point a and sweeps up attempting to lock. if lock is not established during the up sweep, the vco is then swept down. the probability of locking within one cycle period is greater than 0.999. if the system does not lock within one cycle period, it attempts to lock in the subsequent cycle. the average sweep time, (tswp) is determined by the loop filter component (clf1) and the charge pump current (icp): the nominal sweep time is approximately 121 s when clf1 = 15nf and icp = 165 a (rvco = 365 ). an internal system clock determines tsys (see section 3.2.3 logic circuit ). 3.2.3 logic circuit the gs7025 is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. that is, the system clock is completely independent of the incoming data rate. the system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the pll.the period of the system clock is set by the cosc capacitor and is: the recommended value for tsys is 450 s (cosc = 4.7nf) v lf t swp t c y c le t c y c le = t swp + t sys t sys a t swp 4 c lf 1 3 i cp - - - - - - - - - - - - - - = t sys 9. 610 4 c osc onds sec [] =
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 16 of 23 3.2.4 locking the gs7025 indicates valid lock when the following three conditions are satisfied: 1. input data is detected. 2. the incoming data signal and the pll clock are phase locked. 3. the system is not locked to an integer-multiple harmonic of a 270mb/s smpte 259m-c signal. the gs7025 defines the presence of input data when at least one data transition occurs every 1 s. the gs7025 assumes that it is not locked to a harmonic if the pattern ?101? or ?010? (in the reclocked data stream) occurs at least once every tsys/3 seconds. using the recommended component values, this corresponds to approximately 150 s. in a harmonically locked system, all bit cells are double clocked and the above patterns become ?110011? and ?001100?, respectively. 3.2.4.1 lock time synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). when input data to the gs7025 is removed, the gs7025 latches the current state. therefore, when data is reapplied, the gs7025 begins the lock procedure at the previous locked data rate. as a result, in synchronous switching applications, the gs7025 locks very quickly. the nominal lock time depends on the switching time and is summarized in table 3-2 . to acquire lock, the frequency acquisition circuit may have to sweep over an entire cycle depending on initial conditions. maximum lock time is 2tcycle + 2tsys. the nominal value of tcycle for the gs7025 operating in a typical smpte 259m-c application is approximately 1.3ms. the gs7025 has a dedicated lock output (pin 39) indicating when the device is locked. note: in synchronous switching applications where the switching time is less than 0.5 s, the lock output is not de-asserted and the data outputs are not muted. 3.2.4.2 dvb-asi design note: for dvb-asi applications having significant instances of few bit transitions or when only k28.5 idle bits are transmitted, the wide-band pll in the table 3-2: lock time switching time lock time <0.5s 10s 0.5s - 10ms 2t sys >10ms 2t cycle + 2t sys
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 17 of 23 gs7025 may lock at 243mhz being the first 27mhz sideband below 270mhz. in this case, when normal bit density signals are transmitted, the pll will correctly lock onto the proper 270mhz carrier. 3.2.5 output data muting the gs7025 internally mutes the sdo and sdo outputs when the device is not locked. when muted, sdo/sdo are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. the output data muting timing is shown in figure 3-5 . figure 3-5: output data muting timing 3.2.6 clock enable when clk_en is high, the gs7025 sco/sco outputs are enabled. when clk_en is low, the sco/sco outputs are placed in a high-impedance state and float to vcc. disabling the clock outputs results in a power savings of 10%. it is recommended that the clk_en input be hard wired to the desired state. for applications which do not require the clock output, connect clk_en to ground and connect the sco/sco outputs to vcc. 3.2.7 stressful data patterns all pll's are susceptible to stressful data patterns which can introduce bit errors in the data stream. pll's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densities for a long period of time). the gs7025 is designed to operate with low data transition densities such as the smpte 259m-c pathological signal (data transition density = 0.05). 3.3 i/o description 3.3.1 high speed analog inputs (sdi/ sdi ) sdi/sdi are high-impedance inputs which accept differential or single-ended input drive. figure 3-6 shows the recommended interface when a single-ended serial digital signal is used. lock ddi sdo valid data no data transitions valid data outputs muted
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 18 of 23 figure 3-6: high s peed digital inputs (ddi/ ddi ) ddi/ddi are high-impedance inputs which accept differential or single-ended input drive. two conditions must be observed when interfacing to these inputs: 1. input signal amplitudes are between 200 and 2000mv. 2. the common mode input voltage range is as specified in table 2-1: dc electrical characteristics . commonly used interface examples are shown in figure 3-7 , figure 3-8 & figure 3-9 . figure 3-7 illustrates the simplest interface to the gs7025 digital inputs. in this example, the driving device generates the pecl level signals (800mv amplitudes) having a common mode input range between 0.4 and 4.6v. this scheme is recommended when the trace lengths are less than 1in. the value of the resistors depends on the output driver circuitry. figure 3-7: digital inputs - simple interface when trace lengths become greater than 1in, controlled impedance traces should be used. the recommended interface is shown in figure 3-8 . in this case, a parallel resistor (rload) is placed near the gs7025 inputs to terminate the controlled impedance trace. the value of rload should be twice the value of the characteristic impedance of the trace. in addition, place series resistors (rsource) near the driving chip to serve as source terminations. they should be equal to the value of the trace impedance. assuming 800mv output swings at the driver, rload = 100 , rsource = 50 and zo = 50 . figure 3-8: digital inputs - controlled impedance interface figure 3-9 shows the recommended interface when the gs7025 digital inputs are driven single-endedly. in this case, the input must be ac-coupled and a matching resistor (zo) must be used. sdi gs7025 sdi 75 10nf 10nf 75 113 ddi ddi z o gs7025 ddi ddi gs7025
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 19 of 23 figure 3-9: digital inputs - single-ended input interface when the ddi and the ddi inputs are not used, saturate one input of the differential amplifier for improved noise immunity. to saturate, connect either pins 44 and 1 or pins 2 and 3 to vcc. leave the other pair floating. 3.3.2 high speed outputs (sdo/ sdo and sco/ sco ) sdo/sdo and sco/sco are current mode outputs that require external pullup resistors (see figure 3-10 ). to calculate the output sink current, use the following relationship: output sink current = output signal swing / pullup resistor a diode can be placed between vcc and the pullup resistors to reduce the common mode voltage by approximately 0.7v. when the output traces are longer than 1in, controlled impedance traces should be used. the pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75 ). figure 3-10: high-speed outputs with external pullups ddi ddi r source r load r source z o z o gs7025 v cc sdo sdo sco sco 75 75 v cc 75 75 gs7025
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 20 of 23 4. application information 4.1 typical application circuit figure 4-1: gs 7025 typical application c ircuit sdo sdo v ee sco sco v ee n c n c 270 n c gs7025 top view agc+ v cc v ee lf+ lfs lf- v ee r vco _rtn r vco cbg v cc ddi ddi v cc_75 v cc v ee sdi sdi v cc v ee cd_adj agc- v cc_75 oem_test mod a/d ssi/cd lock c osc v ee clk_en v cc v ee v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc 4 x 75 see note 2 to gs9020 1.8k 15n 0.1 0.1 3.3p 3 6 5 (1 % ) 10k 75 37.5 75 10n 10n 75 100k pot (optional) 100p power supply d e c ouplin g c apa c itors are not shown. v ee 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 2 6 25 24 23 12 13 14 15 1 6 17 18 19 20 21 22 44 43 42 41 40 39 38 37 3 6 35 34 all resistors in ohms, all c apa c itors in mi c rofara d s, unless otherwise state d . notes 1. it is re c ommen d e d that the ddi/ddi input are not d riven when the sdi/sdi inputs are b ein g use d . this minimizes c rosstalk b etween the ddi/ddi an d sdi/sdi inputs an d maximizes performan c e. 2. these resistors are not nee d e d if the internal pull-up resistors on the gs9020 are use d . 3. it is re c ommen d e d that for new d esi g ns vco c omponents shoul d b e returne d to the r vco_rtn pin for improve d g roun d b oun c e immunity. v cc 4n7 v cc 15nh v cc v cc v cc from gs9024 see note 1
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 21 of 23 5. package & ordering information 5.1 package dimensions 10.00 0.10 13.20 0.25 pin 1 10.00 0.10 0.80 bsc 0.45 max 0.30 min 13.20 0.25 2.20 max 1.85 min 0.35 max 0.15 min 2.55 max 0.23 max. 1. 6 0 ref 0.3 max. radius 0.13 min. radius 0.88 nom. 0.20 min 5 to 1 6 5 to 1 6 7 max 0 min 0 min 44 pin mqfp all d imensions in millimetres
gs7025 pro-linx? serial digital receiver data sheet 13813 - 7 october 2009 22 of 23 5.2 solder reflow profiles the gs7025 is available in a pb-free package. it is recommended that the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 5-1 . figure 5-1: maximum pb-free s older reflow profile 5.3 ordering information 25c 150c 200c 217c 2 6 0c 250c time temperature 8 min. max 6 0-180 se c . max 6 0-150 se c . 20-40 se c . 3c/se c max 6 c/se c max part number package temperature range gs 7025 gs 7025- c qme3 44 pin mqfp tray 0 c to 70 c
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